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Six Ping

Combined two parallel clock dividers/counters.

(6 Votes)
hlmm
1.0 (Updated 11 months ago)
318.7kB
August 06, 2018
Reaktor 6
Blocks User Blocks

DESCRIPTION

Upper part: Incoming clock -> divider (upper knob, value on left) -> counter (second knob, value on right). Left upper lamp monitors the upper part's output.

Lower part: Incoming clock -> divider (lowest knob, value on left) -> counter (third knob, value on right). Left lower lamp monitors lower part's output.

Central part: first switch is syncing lower divider to upper (on each impulse from upper divider the lower is reset); second switch enables "cancelling" - if both outputs give gate, they cancel each other - nothing is passed to final output. Lamp on the right monitors final clock output.