It seems the primary iterator does its thing between clock cycles. Each iteration is a mathematical process and the timing between steps is related to the mathematical process itself. Therefore the mathematical routine can be written in core. What i don't understand is how each iterations output is heard or accepted in between clock cycles. I have never used the module but it seems in reaktor any input is latched during the next clock cycle. In REAKTOR, iteration can be used to generate a large number of events that are processed simultaneously, but are treated as if they came one after the other. This technique is very useful when using Modules which behave like arrays (like the Multi Display) From the above paragraph taken from the manual it seems multiple events can be triggered in between the serial clock. This is new to me as I was under the impression all event triggers were processed sequentially after the start of the next clock. Once the cpu has processed the entire ensemble it idles and waits to process the new data on the next clock. Obviously every wired connection has the new value latched in memory during the waiting period. Using a switch to detach a wire forces the compiler to created and run a new routing so you can interrupt the process with switches. They are bad news and may eventually be discontinued with the new bundle concepts that turn modules on and off.